1. Technical Field
The present invention relates to a semiconductor system, and more particularly, to a semiconductor memory apparatus, and a set program control circuit and a program method therefor.
2. Related Art
A PCRAM (phase change RAM) is a memory apparatus which uses a phase change characteristic of a specified substance constituting a memory cell. A phase change substance may be converted into an amorphous state or a crystalline state depending upon a temperature condition, and may include, for example, a chalcogenide-based alloy. A representative phase change substance includes a Ge2Sb2Te5 (hereafter referred to as a ‘GST’) substance which comprises germanium, antimony and tellurium.
Most substances have different melting points and crystallization temperatures, and their degree of crystallization may vary depending upon a cooling time and a cooling temperature. This may serve as a unique characteristic of a substance. In particular, a GST substance may be more clearly distinguished between the amorphous state and the crystalline state than other substances.
FIG. 1 is a graph for explaining phase changes of a general phase change substance depending upon a temperature. A GST substance will be used as an example.
When GST is applied with a high temperature equal to or greater than the melting point of GST for a predetermined time (several tens to several hundreds nanoseconds [ns]) and is quenched for a preset time Tq, the amorphous state of the GST is maintained as it is, and a resistance value becomes several hundreds kilohms (kΩ) to several megohms (MΩ).
Also, if the GST is maintained at a crystallization is temperature for a preselected time (several hundreds ns to several microseconds [μs]) and is then cooled, the GST is converted into the crystalline state and the resistance value becomes several kΩ to several tens kΩ. As a time for maintaining the crystallization temperature is lengthened, the crystalline state improves and accordingly, the GST has a smaller resistance value.
FIG. 2 is another graph for explaining phase changes of the general phase change substance depending upon a temperature. Similarly, the GST substance will be used as an example.
FIG. 2 shows an example in which the GST is crystallized by applying a temperature near the melting point of GST for a predetermined time, and slowly cooling the GST. Even in this case, the resistance value of the GST becomes several kΩ to several tens kΩ, and as a cooling time is lengthened, the crystalline state improves. Also, a crystallization time is shortened when compared to FIG. 1.
In order to use such a characteristic of the GST, heat may be directly applied to the GST; or Joule's heat may be electrically generated by current flow through a conductor or a semiconductor to convert the GST between the amorphous state and the crystalline state.
While FIGS. 1 and 2 show general operations of the phase change memory apparatus, the method of FIG. 2 is mainly used since a set data program time, that is, a time required for crystallizing the GST is short.
FIG. 3 is a configuration diagram of a cell array of a is conventional phase change memory apparatus.
Referring to FIG. 3, each memory cell MC is constituted by a phase change substance GST and a switching element which are connected between a word line WL and a bit line BL.
Program operations of a phase change memory apparatus will be described below with reference to FIG. 4.
FIG. 4 is a configuration diagram of a conventional phase change memory apparatus.
Referring to FIG. 4, a phase change memory apparatus 1 includes a program pulse generation block 11, a write driver 12, and a memory block 13.
The program pulse generation block 11 is configured to generate a first write control signal RESETEN and second write control signals SETP<0:n> in response to a programming enable signal PGMP. The program pulse generation block 11 provides the first write control signal RESETEN and the second write control signals SETP<0:n> to the write driver 12. Further, when the operation of generating the first write control signal RESETEN and the second write control signals SETP<0:n> is completed, the program pulse generation block 11 generates a program completion signal PGMNDP and transmits the program completion signal PGMNDP to a controller.
The write driver 12 is configured to be driven in response to a write enable signal WDEN. The write driver 12 is provided with the first write control signal RESETEN and the second write control signals SETP<0:n>, and provides program current I_PGM to the memory block 13 in response to data DATA to be programmed and bit line select switch control signals YSW<0:m>.
Accordingly, in the memory block 13, as the resistant state of a GST is changed depending upon the level of the data DATA to be programmed, the data DATA can be recorded.
FIG. 5 is a block diagram showing an example program pulse generation block shown in FIG. 4.
Referring to FIG. 5, the program pulse generation block 11 is configured to include an initial pulse generation unit 111, a reset pulse generation unit 113, and a quenching pulse generation unit 115.
The initial pulse generation unit 111 is configured to generate a period setting signal QSSETP in response to the programming enable signal PGMP which is provided from the controller. The period setting signal QSSETP is a signal which determines a time to supply heat near a melting point to the GST. The initial pulse generation unit 111 enables the period setting signal QSSETP after counting a preset time in response to the programming enable signal PGMP.
The reset pulse generation unit 113 is configured to generate the first write control signal RESETEN in response to the programming enable signal PGMP and a reset signal IRSTP which is generated by delaying the period setting signal QSSETP by a predefined time.
The quenching pulse generation unit 115 is configured to generate the second write control signals SETP<0:n> which have is different enable periods, in response to the programming enable signal PGMP and the period setting signal QSSETP. Further, the quenching pulse generation unit 115 generates a program completion signal PGMNDP when the generation of the second write control signals SETP<0:n> is completed.
According to such a configuration, the reset pulse generation unit 113 generates the first write control signal RESETEN during a period from after the programming enable signal PGMP is enabled to when the reset signal IRSTP is enabled. The quenching pulse generation unit 115 enables the second write control signals SETP<0:n> at the same levels until the period setting signal QSSETP is enabled, and generates the second write control signals SETP<0:n> after the period setting signal QSSETP is generated.
FIG. 6 is a timing diagram explaining program operations of the conventional phase change memory apparatus.
As a program command PGM is applied, the programming enable signal PGMP is generated from the controller. Accordingly, the initial pulse generation unit 111 operates and generates an internal clock enable signal IPWEN. Then, after an internal clock ICK is generated, counting codes Q<0:3> are generated by counting the preset time, and when the counting is completed, the period setting signal QSSETP is generated.
The reset pulse generation unit 113 enables the first write control signal RESETEN in response to the programming enable signal PGMP, and disables the first write control signal RESETEN as the reset signal IRSTP is enabled. The reset signal IRSTP is generated by delaying the period setting signal QSSETP by the predefined time. During a period in which the first write control signal RESETEN is enabled, programming current is generated from the write driver 12 and is provided to a bit line BL0.
The quenching pulse generation unit 115 generates a count enable signal CKEN (CNTENB) and an internal clock QSCK in response to the period setting signal QSSETP. Accordingly, the second write control signals SETP<0:3> which have different enable periods are generated. When generation of the second write control signal SETP<0:3> is completed, a quenching pulse completion signal QSND is disabled, and then, when a reset signal QSRSTP is enabled, the program completion signal PGMNDP is outputted. In this case, the current driving force of the write driver 12 is sequentially damped according to the enable periods of the second write control signals SETP<0:3>, and a quenching pulse is provided to the GST.
In a program operation, a word line maintains a high potential (equal to or greater than VCC) when a word line select switch is in a disabled state, and is discharged to the level of a ground voltage as the word line select switch is enabled. A current path is formed via a bit line that is selected by the write driver 12. The current path is formed by the write driver 12 through a bit line select switch, the bit line, a switching element and the GST to the word line.
When the current path is formed in this way, the amount of is current driven by the write driver 12 is determined according to the first write control signal RESETEN or the second write control signals SETP<0:n> depending upon a data level (0/1) to be programmed, and the program current is provided to the memory cell through the bit line. For example, when assuming that an amount of current provided by the first write control signal RESETEN is 100%, an amount of current provided to the memory cell when all of the second write control signals SETP<0:3> are enabled is controlled to a rate of 30 to 90%.
In the program operation, the current provided through the bit line is provided in a rectangular type in the case of reset data. In the case of set data, the current is provided initially in a type similar to a rectangular type but is then provided by being reduced into a step type by the second write control signals SETP<0:n>.
Therefore, in the case where set data and reset data are simultaneously programmed, a time required for a program operation is determined by a set data program time that is long when compared to a reset data program time.
Meanwhile, a phase change memory apparatus tends to be used in place of a flash memory. In this case, a memory apparatus performs corresponding operations by receiving a program command and an erase command through a flash memory interface. However, the phase change memory apparatus programs set data or reset data only according to a write command. Therefore, when it is necessary to operate the phase change memory apparatus by the flash memory interface, if an erase command is applied, the phase change memory apparatus does not perform any operation and is in an idle mode.